Modeling Diode Reverse Breakdown Voltages in LTSpice

The included models in LTSpice do not include reverse breakdown. In order to model the reverse breakdown "vrev" can be specified in the diode model. For this example, create a new schematic and call the diode "mydiode". Insert the .model directive to add the reverse breakdown. Below, I used all the standard parameters for the 1N4148 and added vrev=50. The vrev specifies the reverse breakdown at -50V. Many other diode properties can be defined in the model including the non-linear characteristics of the breakdown.

Forward and reverse breakdown and current limitations can be modeled by using a more sophisticated model. Using the model below, forward and reverse current limiting can be observed.

.model mydiode D(vrev=40 Ibv=20nA BV=40 Ibv=1e-10 Is=1e-7 Rs=10 Tt=2n Ilimit=5mA Vpk=40 Revilimit=5mA)

Adding a LM741 Op Amp Model to LTSpice

Simulating operational amplifiers in LTSpice using non-ideal characteristics is desirable for students to understand op amp AC and DC limitations. Many student projects require the use of the classic LM741 op amp. The following steps can be followed to get the LM741 model into LTSpice for simulation.

Step 1: Obtain the spice model for the LM741 (see complete model below)

Step 2: Copy this model into the LTSpice sub directory. The file must be given a *.sub extension and not a *.txt extension. Make sure to save the file as “all file types” with the .sub extension. Save the file as LM741.sub. The directory is typically: C:\Program Files\LTC\LTspiceIV\lib\sub

Step 3: Start up LTSpice, insert the op amp2 component. Right click on the symbol and change the value to LM741.

Step 4: Add the spice directive to the schematic using the .op. Add “.lib LM741.sub” to the schematic.

Step 5: You are now ready to run simulations with the LM741.

Spice model below:

*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.

*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal

*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com

*//////////////////////////////////////////////////////////
*LM741 OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM741 1 2 99 50 28
*
*Features:
*Improved performance over industry standards
*Plug-in replacement for LM709,LM201,MC1439,748
*Input and output overload protection
*
****************INPUT STAGE**************
*
IOS 2 1 20N
*^Input offset current
R1 1 3 250K
R2 3 2 250K
I1 4 50 100U
R3 5 99 517
R4 6 99 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=2.55 MHz
C4 5 6 60.3614P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 1.6MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 1E-3 1
*Input offset voltage.^
R8 99 49 40K
R9 49 50 40K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 1.63
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 2.1E-3
*Fp1=5 Hz
R5 98 9 95.493MEG
C3 98 9 333.33P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.3052E-15
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=300 Hz
G4 98 16 3 49 3.1623E-8
L2 98 17 530.5M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 450U 1
E1 99 23 99 15 1
R16 24 23 25
D5 26 24 DX
V6 26 22 0.65V
R17 23 25 25
D6 25 27 DX
V7 22 27 0.65V
V5 22 21 0.18V
D4 21 15 DX
V4 20 22 0.18V
D3 15 20 DX
L3 22 28 100P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX NPN(BF=625)
*
.ENDS
*$[/url]

Getting Started with LTSpice

LTSpice is a great free circuit simulator. The software and introduction videos can be found at: www.cmosedu.com

New Mac Mini

I finally took the plunge and picked up a Mac. I'm recording a brief diary of pros/cons from my journey: 

Mac Impressions Diary

68HCS12 Heartbeat

It's often useful to have a flashing LED in embedded systems to verify the system is 'running' and healthy. I coded up a 500ms heartbeat using the Motorolla 68HCS12 in C. See below.

#include "vectors12.h"
#include "ioregs12.h"
#include "bits.h" // custom header containing bit values in hex

#define INTERRUPT void __attribute__ ((interrupt))
#define sei() __asm__ __volatile__ ( "sei" )
#define cli() __asm__ __volatile__ ( "cli" )
#define wai() __asm__ __volatile__ ( "wai" )

volatile unsigned int hbcount;

INTERRUPT rti_interrupt(void);

int main(void)
{
// Initialization
sei(); // diable interrupts
UserRTI = (unsigned int) &rti_interrupt;
RTICTL = 0x40; // set RTICTL for 1ms interrupt
CRGINT = BIT8; // enable RTI interrupts
DDRT |= BIT8; // or equal
cli(); // clear interrupt flag

while (1)
{ // idle loop
wai();
};
return 0;
}

INTERRUPT rti_interrupt(void)
{
CRGFLG = 0x80; // acknoledge RTI & clear interrupt flag
hbcount++;
if (hbcount >= 489) // Reset hbcount every 500ms
{
hbcount = 0;
PTT = PTIT ^ BIT8; // exclusive or PTT
}
}

PDP-8 Minicomputer

It's 40 year old technology, but it still pretty cool and complex. I'm working to realize the PDP-8 minicomputer from the early 70s using an FPGA. Stay tuned for progress updates!

Parallel Adder / Multiplier using VHDL

I designed a state machine controller using VHDL. This state machine implemented a parallel adder and multiplier with overflow capability. This project used the Nexys2 board from Digilent. I used Xilinx ISE for the coding and Modelsim for the simulation. For a full report see "Adder / Multiplier in VHDL" under papers.